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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad5516 * 16-channel, 12-bit voltage-output dac with 14-bit increment mode * protected by u.s. patent no. 5,969,657; other patents pending. features high integration: 16-channel dac in 12 mm 12 mm cspbga 14-bit resolution via increment/decrement mode guaranteed monotonic low power, spi , qspi , microwire , and dsp compatible 3-wire serial interface output impedance 0.5 output voltage range 2.5 v (ad5516-1) 5 v (ad5516-2) 10 v (ad5516-3) asynchronous reset facility (via reset pin) asynchronous power-down facility (via pd pin) daisy-chain mode temperature range: ?0 c to +85 c applications level setting instrumentation automatic test equipment optical networks industrial control systems data acquisition low cost i/o functional block diagram r fb 0 reset busy dacgnd agnd dgnd dcen ad5516 dv cc av cc v dd v ss v out 0 r fb 1 v out 1 r fb 14 v out 14 r fb 15 v out 15 r offs r fb dac v bias r offs r fb dac r offs r fb dac r offs r fb dac ref_in pd power-down logic sclk d in d out sync interface control logic 7-bit bus analog calibration loop 12-bit bus mode1 mode2 general description the ad5516 is a 16-channel, 12-bit voltage-output dac. the selected dac register is written to via the 3-wire serial inter- face. dac selection is accomplished via address bits a3?0. 14-bit resolution can be achieved by fine adjustment in incre- ment/decrement mode (mode 2). the serial interface operates at clock rates up to 20 mhz and is compatible with standard spi, microwire, and dsp interface standards. the output voltage range is fixed at 2.5 v (ad5516-1), 5 v (ad5516-2), and 10 v (ad5516-3). access to the feedback resistor in each channel is provided via the r fb 0 to r fb 15 pins. the device is operated with av cc = 5 v 5%, dv cc = 2.7 v to 5.25 v, v ss = ?.75 v to ?2 v, and v dd = +4.75 v to +12 v, and requires a stable 3 v reference on ref_in. product highlights 1. sixteen 12-bit dacs in one package, guaranteed monotonic. 2. available in a 74-lead cspbga package with a body size of 12 mm 12 mm.
rev. b e2e ad5516especifications (v dd = +4.75 v to +13.2 v, v ss = e4.75 v to e13.2 v; av cc = 4.75 v to 5.25 v; dv cc = 2.7 v to 5.25 v; agnd = dgnd = dacgnd = 0 v; ref_in = 3 v; all outputs unloaded. all specifications t min to t max , unless otherwise noted.) parameter 1 a version 2 unit conditions/comments dac dc performance resolution 12 bits integral nonlinearity (inl) 2 lsb max mode 1 differential nonlinearity (dnl) e1/+1.3 lsb max 0.5 lsb typ, monotonic; mode 1 increment/decrement step-size 0.25 lsb typ monotonic; mode 2 only bipolar zero error 7 lsb max positive full-scale error 10 lsb max negative full-scale error 10 lsb max voltage reference ref_in nominal input voltage 3 v input voltage range 3 2.875/3.125 v min/max input current 1 m a max < 1 na typ analog outputs (v out 0e15) output temperature coefficient 3, 4 10 ppm/ sync c tututs busy ut cc s cc s cc s cc s c ut cen c ut cen erreureents s ss cc cc sc cs ss cs cc cc c ss cc cc ss ntes st
rev. b ad5516 e3e ac characteristics (v dd = +4.75 v to +13.2 v, v ss = e4.75 v to e13.2 v; av cc = 4.75 v to 5.25 v; dv cc = 2.7 v to 5.25 v; agnd = dgnd = dacgnd = 0 v; ref in = 3 v. all outputs unloaded. all specifications t min to t max , unless otherwise noted.) parameter 1, 2 a version 3 unit conditions/comments output voltage settling time (mode 1) 4 100 pf, 5 k w load full-scale change ad5516e1 32 s max ad5516e2 32 s max ad5516e3 36 s max output voltage settling time (mode 2) 4 100 pf, 5 k w load, 127 code increment ad5516e1 2.5 s max ad5516e2 3.35 s max ad5516e3 7 s max slew rate 0.85 v/ s typ digital-to-analog glitch impulse 1 nv -s typ 1 lsb change around major carry digital crosstalk 5 nv-s typ analog crosstalk ad5516e1 1 nv-s typ ad5516e2 5 nv-s typ ad5516e3 20 nv-s typ digital feedthrough 1 nv-s typ output noise spectral density @ 10 khz ad5516e1 150 nv/(hz) 1/2 typ ad5516e2 350 nv/(hz) 1/2 typ ad5516e3 700 nv/(hz) 1/2 typ notes 1 see terminology section. 2 guaranteed by design and characterization; not production tested. 3 a version: industrial temperature range e40 busy s t n t u cc ute cur ute cur cn sc sc sc sync escest n st n t sce sync re sync ts e sync tc e busy re sync e e sce sync es sync rescrec scre ut c reset ntes st cc t s tncrcterstcs ss cc cc nncnt n t
rev. b e4e ad5516 timing diagrams t 12 sclk sync din busy reset 12 17 18 t 3 t 7 t 4 t 5 t 2 t 1 t 6 t 9 mode2 t 8 mode1 bit 17 bit 0 lsb msb figure 1. serial interface timing diagram sclk sync d in d out busy bit 17 bit 0 bit 17 bit 0 input word for device n+1 undefined input word for device n input word for device n bit 17 bit 0 t 7 mode2 t 3 t 2 t 1 t 6 t 10 t 5 t 4 t 11 t 8 mode1 lsb msb figure 2. daisy-chaining timing diagram to output pin c l 50pf 200 a i oh 200 a i ol 1.6v figure 3. load circuit for d out timing specifications
rev. b ad5516 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5516 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +17 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?7 v av cc to agnd, dacgnd . . . . . . . . . . . . . . . ?.3 v to +7 v dv cc to dgnd . . . . . . . . . . . . . . . . . . . . . . . .?.3 v to +7 v digital inputs to dgnd . . . . . . . . . . . ?.3 v to dv cc + 0.3 v digital outputs to dgnd . . . . . . . . . . ?.3 v to dv cc + 0.3 v ref_in to agnd, dacgnd . . . . . . ?.3 v to av cc + 0.3 v v out 0?5 to agnd . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v r fb 0?5 to agnd . . . . . . . . . . . . . v ss ?0.3 v to v dd +0 .3 v operating temperature range, industrial . . . . . 40 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature (t j max ) . . . . . . . . . . . . . . . . . . . 150 c 74-lead cspbga package, ja thermal impedance . . . 41 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c time at peak temperature . . . . . . . . . . . . . 10 sec to 40 sec notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide model function output voltage span package option ad5516abc-1 16 dacs 2.5 v 74-lead cspbga ad5516abc-2 16 dacs 5 v 74-lead cspbga ad5516abc-3 16 dacs 10 v 74-lead cspbga eval-ad5516-1eb evaluation board eval-ad5516-2eb evaluation board eval-ad5516-3eb evaluation board
rev. b e6e ad5516 pin configuration a b c d e f g h j k 11 10 9 8 7 6 5 4 3 2 1 top view a b c d e f g h j k 11 10 9 8 7 6 5 4 3 2 1 ll 74-lead cspbga ball configuration cspbga ball cspbga ball cspbga ball cspbga ball cspbga ball number name number name number name number name number name nc = not internally connected a1 nc a2 nc a3 reset busy n cc ut n sync nc nc b nc b nc b nc b cen b n b n b nc b nc b sc b nc b ren c ut c cn c nc c cc c nc r b cn cc nc e ut e nc e n e ut r b n r b r b r b ut r b ut ut ut ut r b ut nc r b r b r b ut r b nc ss ss ut ut r b r b ut nc ut r b ut nc r b ut r b nc nunctnescrtns n n cc s s ss ss s n n cc s cn rnsc ren rctren ut cc r b rr b ut c t sync t sync sc
rev. b ad5516 e7e terminology integral nonlinearity (inl) this is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is expressed in lsbs. differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of e1 lsb maximum ensures monotonicity. bipolar zero error bipolar zero error is the deviation of the dac output from the ideal midscale of 0 v. it is measured with 10...00 loaded to the dac. it is expressed in lsbs. positive full-scale error this is the error in the dac output voltage with all 1s loaded to the dac. ideally the dac output voltage, with all 1s loaded to the dac registers, should be 2.5 v e 1 lsb (ad5516-1), 5 v e 1 lsb (ad5516-2), and 10 v e 1 lsb (ad5516-3). it is expressed in lsbs. negative full-scale error this is the error in the dac output voltage with all 0s loaded to the dac. ideally the dac output voltage, with all 0s loaded to the dac registers, should be e2.5 v (ad5516-1), e5 v (ad5516-2), and e10 v (ad5516-3). it is expressed in lsbs. output temperature coefficient this is a measure of the change in analog output with changes in temperature. it is expressed in ppm/ reset ctc cctc busy t t busy c ute busy ntes t t
rev. b e8e ad5516etypical performance characteristics dac code dnl error (lsb) 1.0 0.6 0.2 e0.2 0 e0.4 e0.6 0.8 0.4 e0.8 e1.0 1000 2000 3000 4000 0 ref_in = 3v t a = 25 c tpc 1. typical dnl plot temperature ( c) error (lsb) 3 e40 1 e1 0 e2 e3 e20 0 20 40 80 2 60 ref_in = 3v bipolar zero error positive fs error negative fs error tpc 4. bipolar zero error and full-scale error vs. temperature v out ( v) 3.0 1.0 0 e1.0 e2.0 2.0 e3.0 time base = 2.5 s/div t a = 25 c ref_in = 3v tpc 7. ad5516e1 full-scale settling time dac code inl error (lsb) 1.0 0.6 0.2 e0.2 0 e0.4 e0.6 0.8 0.4 0 e0.8 e1.0 1000 2000 3000 4000 ref_in = 3v t a = 25 c tpc 2. typical inl plot temperature ( c) v out (v) 0.003 e40 0.002 0.001 e0.001 0 e0.002 e0.003 e20 0 20 40 80 av dd = +12v av ss = e12v ref_in = 3v midscale loaded 60 tpc 5. v out vs. temperature v out pd t a = 25 c ref_in = 3v 5v/div 2v/div 2 s /div tpc 8. exiting power-down to full scale temperature ( c) error (lsb) 2.0 e40 1.0 0 e1.0 e0.5 e1.5 e2.0 e20 0 20 40 80 1.5 0.5 60 inl +ve dnl eve dnl ref_in = 3v tpc 3. typical inl error and dnl error vs. temperature current (ma) v out (v) e6 0.002 e4 e2 0 2 6 4 midscale av dd = +12v av ss = e12v ref_in = 3v t a = 25 c 0.0 e0.002 e0.004 e0.006 e0.008 e0.01 0.004 0.006 0.008 0.01 e8 8 tpc 6. v out source and sink capability 5v busy e0.029 e0.031 e0.032 e0.030 e0.033 t a = 25 c ref_in = 3v calibration time new va l u e 2.5 s/div old va l u e 0v tpc 9. ad5516e1 major code transition glitch impulse
rev. b ad5516 e9e v out (v) frequency 450 350 250 150 200 100 50 400 300 2.4899 2.4896 2.4893 0 tpc 10. ad5516e1 v out repeatability; programming the same code multiple times frequency (%) 30 20 0 e10 0 10 10 ref_in = 3v t a = 25 c lsbs tpc 13. negative full-scale error distribution frequency (%) 40 20 0 e10 0 10 ref_in = 3v t a = 25 c lsbs tpc 12. positive full-scale error distribution 6 4 5 3 0 1000 1500 500 2000 2500 code error (lsb) 3000 3500 4000 2 0 1 ref_in = 3v t a = 25 c tpc 15. accuracy vs. increment step, using all 12 mode 2 bits frequency (%) 40 20 0 e10 0 10 ref_in = 3v t a = 25 c lsbs tpc 11. bipolar error distribution step size error (lsb) 2.5 2.0 1.5 1.0 0.5 0 020406 080 100 120 130 ref_in = 3v t a = 25 c tpc 14. accuracy vs. increment step
rev. b e10e ad5516 00 a3 a2 a1 a0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 msb lsb mode bits address bits data bits figure 4. mode 1 data format 01 a3 a2 a1 a0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 msb lsb mode bits address bits 12 increment bits 10 a3 a2 a1 a0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 msb lsb mode bits address bits 12 decrement bits figure 5. mode 2 data format functional description the ad5516 consists of sixteen 12-bit dacs in a single pack- age. a single reference input pin (ref_in) is used to provide a 3v reference for all 16 dacs. to update a dac?s output voltage, the required dac is addressed via the 3-wire serial interface. once the serial write is complete, the selected dac converts the code into an output voltage. the output amplifiers translate the dac output range to give the appropriate voltage range ( 2.5 v, 5 v, or 10 v) at output pins v out 0 to v out 15. the ad5516 uses a self-calibrating architecture to achieve 12-bit performance. the calibration routine servos to select the appro- priate voltage level on an internal 14-bit resolution dac. busy busy busy n busy sbstc ren t uc reset ttnsectn tc c tren c tc v vdv out ref in n ref in = 225 32 25 3 __ . e . ad5516-2: v vdv out ref in n ref in = 425 32 225 3 __ . e . ad5516-3: v vdv out ref in n ref in = 825 32 425 3 __ . e . w here: d = decimal equivalent of the binary code that is loaded to the dac register, i.e., 0e4095 n = dac resolution = 12 table i illustrates ideal analog output versus dac code. table i. dac register contents ad5516-1 msb lsb analog output, v out 1111 1111 1111 v ref_in 2.5/3 e 1 lsb 1000 0000 0000 0 v 0000 0000 0000 ev ref_in 2.5/3 modes of operation the ad5516 has two modes of operation. mode 1 (mode bits = 00): the user programs a 12-bit data- word to one of 16 channels via the serial interface. this word is loaded into the addressed dac register and is then converted into an analog output voltage. during conversion, the busy sc busy csc busy e csb ct c bbsb bbsb bbte c t c sbbb t tc tc
rev. b ad5516 e11e sync sync scsc sync sync sc cs ccen csc tsc sync ut tsc b n e t nn s sync t sync sync c reset t reset t reset t t busy busy sc busy c sc busy crrcessrntercn t s ssrcs tssrcs t sync sc c adsp-2106x user manual for information on clock and frame sync frequencies for the sport register and contents of the tdiv and rdiv registers. the user must allow 200 ns (min) between two consecutive mode 2 writes in standalone mode and 400 ns (min) between two consecutive mode 2 writes in daisy-chain mode. during a mode 2 operation the busy s en t cs e sernterce t sscrres t t t sync sync sbsbt c t sc sc c c c bb tc sync unctn s c sync sync t sync sync sc scen sync sc sc c
rev. b e12e ad5516 a data transfer is initiated by writing a word to the tx register after the sport has been enabled. in write sequences, data is clocked out on each rising edge of the dsp?s serial clock and clocked into the ad5516 on the falling edge of its sclk. the sport transmit control register should be set up as follows: dtype = 00, right justify data iclk = 1, internal serial clock tfsr = 1, frame every word intf = 1, internal frame sync ltfs = 1, active low frame sync signal lafs = 0, early frame sync sendn = 0, data transmitted msb first slen = 10011, 18-bit data-words (slen = serial word) figure 6 shows the connection diagram. ad5516 * adsp-2106x * sync d in sclk tfs dt sclk * additional pins omitted for clarity figure 6. ad5516 to adsp-2106x interface ad5516 to mc68hc11 the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)?see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the ad5516, the mosi output drives the serial data line (d in ) of the ad5516. the sync c sync cs scs c sb srrc cc sync sc n c sc s tnnsttercrty cc cc tccss scbct sscr sscns pic16/17 microcontroller user manual . in this example, i/o port ra1 is being used to provide a sync t cc sc n sync scrc src r tnnsttercrty cc c t t t scr sync tc sbsb c sc n sync t r tnnsttercrty c rt tc c utr c
rev. b ad5516 e13e application circuits the ad5516 is suited for use in many applications, such as level setting, optical, industrial systems, and automatic test applications. in level setting and servo applications where a fine-tune adjust is required, the mode 2 function increases resolution. the following figures show the ad5516 used in some potential applications. ad5516 in a typical ate system the ad5516 is ideally suited for the level setting function in automatic test equipment. a number of dacs are required to control pin drivers, comparators, active loads, parametric mea- surement units, and signal timing. figure 10 shows the ad5516 in such a system. dac stored data and inhibit pattern period generation and delay timing dacs formatter compare register system bus dac dac dac dac active load parametric measurement unit system bus dac dac comparator dut driver figure 10. ad5516 in an ate system ad5516 in an optical network control loop the ad5516 can be used in optical network control applica- tions that require a large number of dacs to perform a control and measurement function. in the example shown in figure 11, the outputs of the ad5516 are fed into amplifiers and used to con trol actuators that determine the position of mems mirrors in an optical switch. the exact position of each mirror is mea sured and the readings are multiplexed into an 8-channel, 14-bit adc (ad7865). the increment and decrement modes of the dacs are useful in this application as they allow 14-bit resolution. the control loop is driven by an adsp-2106x, a 32-bit sharc dsp. ad5516 0 15 mems mirror array 0 15 s e n s o r s adg609 2 0 7 ad7865 ad8644 2 adsp-2106x figure 11. ad5516 in an optical control loop ad5516 in a high current circuit access to the feedback loop of the ad5516 amplifier provides greater flexibility, e.g., it enables the user to configure the device as a digitally programmable current source or increase the out- put drive current. see figure 12. note that v dd must be chosen so that the dac output has enough headroom to drive the bjt ~ 0.7 v above the maximum output voltage. ad5516-1 v dd v dac v out 0 r fb 0 r v x = ? 2.5v to +2.5v v dd v ss x figure 12. ad5516 in a high current circuit note it is not intended that the r fb nodes be used to alter amplifier gain or for force/sense in remote sense applications. power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad 5516 is mounted should be designed so that the analog and digital sec tions are separated and confined to certain areas of the board. if the ad 5516 is in a system w here multiple d evices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (av cc 1, av cc 2), it is recommended to tie those pins together. the ad5516 should have ample supply bypassing of 10 m f in parallel with 0.1 m f on each supply located as closely to the package as possible, ideally right up against the device. the 10 m f capacitors are the tantalum bead type. the 0.1 m f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5516 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the d in and sclk lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). it is essential to minimize noise on refin. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro- strip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process.
rev. b e14e ad5516 outline dimensions 74-lead chip scale ball grid array [cspbga] (bc-74) dimensions shown in millimeters a b c d e f g h j k l 11 10 9 8 7 6 5 4 3 2 1 1.00 bsc 1.00 bsc bot tom view a1 top view detail a 1.70 max 12.00 bsc sq 10.00 bsc sq a1 corner index area seating plane detail a ball diameter 0.30 min 0.70 0.60 0.50 0.20 max coplanarity compliant to jedec standards mo-192abd-1
rev. b ad5516 ?5 revision history location page 8/03?ata sheet changed from rev. a to rev. b. updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to tpc 14 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 addition of tpc 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to mode 2 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8/02?ata sheet changed from rev. 0 to rev. a. term lfbga updated to cspbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . global changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 addition to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to digital-to-analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 added ad5516 in a high current circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 added figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 updated bc-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
c02792??/03(b) ?6

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